Work in progress - Mastery of digital logic skills through practice using java applets

Our electrical and computer engineering students at Northern Arizona University often have difficulty successfully applying their digital logic skills to subsequent courses. Colleagues at other universities have expressed similar experiences. To provide more extensive practice and immediate student feedback, we have been developing a set of Java applets to address key digital logic skills. Two such applets have been introduced in our logic course to date. The first targets Karnaugh maps and their use in minimizing Boolean equations. The second centers on the expression of timing diagrams derived from propagation delays and logic circuit topology. Preliminary results obtained during fall semester 2003 have shown encouraging signs of improved mastery of the targeted skills. These applets will be deployed in fall 2004 on a larger scale, including at least one partner university, for a more complete assessment of effectiveness.