TY - GEN
T1 - Via-programmable expanded universal logic gate in MCML for structured ASIC applications
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
AU - Brauer, Elizabeth J.
AU - Hatirnaz, I.
AU - Badel, S.
AU - Leblebici, Y.
PY - 2006
Y1 - 2006
N2 - This paper presents a via-programmable expanded universal logic gate in MOS Current-Mode Logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the first via mask, while Metal3 and higher levels are used for cell-to-cell interconnections. Thus the cell is suitable for a structured ASIC design methodology. The circuit was used to create a functional cell library which can implement a wide range of functions. The cells are simulated to characterize delays, and a design strategy is proposed for large scale integration.
AB - This paper presents a via-programmable expanded universal logic gate in MOS Current-Mode Logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the first via mask, while Metal3 and higher levels are used for cell-to-cell interconnections. Thus the cell is suitable for a structured ASIC design methodology. The circuit was used to create a functional cell library which can implement a wide range of functions. The cells are simulated to characterize delays, and a design strategy is proposed for large scale integration.
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M3 - Conference contribution
AN - SCOPUS:34547308804
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2893
EP - 2896
BT - ISCAS 2006
Y2 - 21 May 2006 through 24 May 2006
ER -