Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Armin Tajalli; Eric Vittoz; Yusuf Leblebici; Elizabeth J. Brauer

doi:10.1109/ESSCIRC.2007.4430304

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Armin Tajalli, Eric Vittoz, Yusuf Leblebici, Elizabeth J. Brauer

Informatics, Computing, and Cyber Systems, School of

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Scopus citations

Abstract

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 μm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

Original language	English (US)
Title of host publication	ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
Pages	304-307
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2007.4430304
State	Published - 2007
Event	ESSCIRC 2007 - 33rd European Solid-State Circuits Conference - Munich, Germany Duration: Sep 11 2007 → Sep 13 2007

Publication series

Name	ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Other

Other	ESSCIRC 2007 - 33rd European Solid-State Circuits Conference
Country/Territory	Germany
City	Munich
Period	9/11/07 → 9/13/07

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ESSCIRC.2007.4430304

Cite this

Tajalli, A., Vittoz, E., Leblebici, Y., & Brauer, E. J. (2007). Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. In ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference (pp. 304-307). Article 4430304 (ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2007.4430304

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. / Tajalli, Armin; Vittoz, Eric; Leblebici, Yusuf et al.
ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference. 2007. p. 304-307 4430304 (ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tajalli, A, Vittoz, E, Leblebici, Y & Brauer, EJ 2007, Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. in ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference., 4430304, ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference, pp. 304-307, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, Munich, Germany, 9/11/07. https://doi.org/10.1109/ESSCIRC.2007.4430304

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abstract = "This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 μm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.",

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AB - This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 μm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

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Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

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