A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18m CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1nA, achieving sufficiently high gain (>3) over a wide frequency range.
|Original language||English (US)|
|Number of pages||3|
|State||Published - 2007|
ASJC Scopus subject areas
- Electrical and Electronic Engineering