Ultra-low power subthreshold current-mode logic utilising PMOS load device

A. Tajalli; E. Vittoz; Y. Leblebici; E. J. Brauer

doi:10.1049/el:20071208

Ultra-low power subthreshold current-mode logic utilising PMOS load device

A. Tajalli, E. Vittoz, Y. Leblebici, E. J. Brauer

Informatics, Computing, and Cyber Systems, School of

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18m CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1nA, achieving sufficiently high gain (>3) over a wide frequency range.

Original language	English (US)
Pages (from-to)	911-913
Number of pages	3
Journal	Electronics Letters
Volume	43
Issue number	17
DOIs	https://doi.org/10.1049/el:20071208
State	Published - 2007

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:20071208

Cite this

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title = "Ultra-low power subthreshold current-mode logic utilising PMOS load device",

abstract = "A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18m CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1nA, achieving sufficiently high gain (>3) over a wide frequency range.",

author = "A. Tajalli and E. Vittoz and Y. Leblebici and Brauer, {E. J.}",

year = "2007",

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AU - Leblebici, Y.

AU - Brauer, E. J.

PY - 2007

Y1 - 2007

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AB - A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18m CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1nA, achieving sufficiently high gain (>3) over a wide frequency range.

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Ultra-low power subthreshold current-mode logic utilising PMOS load device

Abstract

ASJC Scopus subject areas

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