Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP

Keyphrases

• Ultra-low Power 100%
• Power Delay Product 100%
• Subthreshold 100%
• Source-coupled Logic 100%
• 32-bit 100%
• Pipelined Adder 100%
• Logic Gates 50%
• CMOS Technology 25%
• Logic Circuit 25%
• Low Power Consumption 25%
• Small Area 25%
• Delay Performance 25%
• Power Delay Profile 25%
• Very Low Power 25%
• Area Overhead 25%
• Measurement Results 25%
• System Energy Consumption 25%
• Keeper 25%
• Consumption Area 25%
• Cross-coupled Differential Pairs 25%
• Activity Rate 25%
• Pipeline Method 25%

Engineering

• Logic Gate 100%
• Adders 100%
• Power Stage 100%
• Logic Circuit 50%
• Energy Systems 50%
• Differential Pair 50%
• Low Power Consumption 50%
• Additional Cost 50%
• Area Overhead 50%