Abstract
Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology, it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.
Original language | English (US) |
---|---|
Pages (from-to) | 893-908 |
Number of pages | 16 |
Journal | IEEE Transactions on Parallel and Distributed Systems |
Volume | 9 |
Issue number | 9 |
DOIs | |
State | Published - 1998 |
Externally published | Yes |
Keywords
- 3D mesh
- 3D packaging
- Adaptive routing
- Deadlock freedom
- MPP networks
- Offset cube
- Optical interconnect
- Through-wafer signaling
- Ultra-compact systems
ASJC Scopus subject areas
- Signal Processing
- Hardware and Architecture
- Computational Theory and Mathematics