Switching Layer Design and Its Influence on RRAM Power Efficiency

Reducing operating power while maintaining a robust read margin remains a key challenge for resistive random-access memory devices. In this work, planar indium tin oxide (ITO)/tungsten oxide (WO_x)/ITO resistive random-access memory devices incorporating porous helical WOx active layers, fabricated using a glancing angle deposition method, are compared with conventional thin-film architectures to evaluate how active-layer geometry influences low-power switching behavior. While both device types exhibit comparable operation at a compliance current limit of 5 mA, only the helical devices sustain reproducible bipolar switching at a reduced compliance of 500 μA. In this low-current regime, switching power is reduced by nearly an order of magnitude while the memory window increases by approximately 5–7 times due to the selective suppression of high-resistance-state leakage. These results demonstrate that active-layer geometry enables a low-power, high-margin operating regime inaccessible to thin-film devices, providing a scalable pathway for energy-efficient resistive random-access memory devices in transparent, flexible, and high-surface-area systems.