Sub-70 PS full adder in 0.18 μm CMOS current-mode logic

Elizabeth J. Brauer; Yusuf Leblebici

Sub-70 PS full adder in 0.18 μm CMOS current-mode logic

Elizabeth J. Brauer, Yusuf Leblebici

Informatics, Computing, and Cyber Systems, School of

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This paper presents a single-bit full adder in MOS Current-Mode Logic with fast delays and low power compared to configurations previously reported. Our low power full adder exhibits post-layout carry-in to carry-out delays of less than 70 ps and can be utilized as building blocks in very high performance datapaths. The circuits are designed and simulated in a 0.18 μm CMOS process and V_DD of 1.8 V.

Original language	English (US)
Title of host publication	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
Editors	M.H. Rashid
Pages	482-486
Number of pages	5
State	Published - 2004
Event	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems - Clearwater Beach, FL, United States Duration: Nov 28 2004 → Dec 1 2004

Publication series

Name	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Other

Other	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
Country/Territory	United States
City	Clearwater Beach, FL
Period	11/28/04 → 12/1/04

Keywords

CML
CMOS
Current-mode logic
Full adder

ASJC Scopus subject areas

General Engineering

Cite this

Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. / Brauer, Elizabeth J.; Leblebici, Yusuf.
Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. ed. / M.H. Rashid. 2004. p. 482-486 449-101 (Proceedings of the IASTED International Conference on Circuits, Signals, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Brauer, EJ & Leblebici, Y 2004, Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. in MH Rashid (ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems., 449-101, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, pp. 482-486, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, United States, 11/28/04.

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AB - This paper presents a single-bit full adder in MOS Current-Mode Logic with fast delays and low power compared to configurations previously reported. Our low power full adder exhibits post-layout carry-in to carry-out delays of less than 70 ps and can be utilized as building blocks in very high performance datapaths. The circuits are designed and simulated in a 0.18 μm CMOS process and VDD of 1.8 V.

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Sub-70 PS full adder in 0.18 μm CMOS current-mode logic

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

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