Abstract
The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for intrachip and interchip communication. An analysis of the impact several architectural and technological parameters have on the optimal network implementation (based on average no-load latency) is presented.
| Original language | English (US) |
|---|---|
| Pages | 165-169 |
| Number of pages | 5 |
| State | Published - 1996 |
| Externally published | Yes |
| Event | Proceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA Duration: Oct 7 1996 → Oct 9 1996 |
Conference
| Conference | Proceedings of the 1996 International Conference on Computer Design, ICCD'96 |
|---|---|
| City | Austin, TX, USA |
| Period | 10/7/96 → 10/9/96 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering