@inproceedings{fb70e199a2a34a5bb1713817b15af002,
title = "Low noise MCML prefix adders using 0.18 μm CMOS technology",
abstract = "This paper presents 3 adders of 8, 16 and 32 bit operands using MOS Current-Mode Logic in a prefix adder architecture with minimum logic levels and fan-out of two. The 32-bit adder exhibits delays of less than 530 ps for nominal conditions with a power supply current spike of only 1.2% of the nominal current. The circuits are designed and simulated in a 0.18 μm CMOS process and VDD of 1.8V.",
keywords = "CMOS, Current-mode logic, Low noise, MCML, Prefix adder",
author = "Brauer, {Elizabeth J.} and Yusuf Leblebici",
year = "2004",
language = "English (US)",
isbn = "0889864551",
series = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",
pages = "467--470",
editor = "M.H. Rashid",
booktitle = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",
note = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems ; Conference date: 28-11-2004 Through 01-12-2004",
}