Low-complexity high-throughput qc-ldpc decoder for 5g new radio wireless communication

Tram Thi Bao Nguyen, Tuy Nguyen Tan, Hanho Lee

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Original languageEnglish (US)
Article number516
Pages (from-to)1-18
Number of pages18
JournalElectronics (Switzerland)
Volume10
Issue number4
DOIs
StatePublished - Feb 2 2021
Externally publishedYes

Keywords

  • 5G new radio standard
  • Channel coding
  • Decoder architectures
  • Quasi-cyclic low-density parity-check (QC-LDPC) codes

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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