TY - GEN
T1 - Improving the power-delay product in SCL circuits using source follower output stage
AU - Tajalli, Armin
AU - Gurkaynak, Frank K.
AU - Leblebici, Yusuf
AU - Alioto, Massimo
AU - Brauer, Elizabeth J.
PY - 2008
Y1 - 2008
N2 - This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.
AB - This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.
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U2 - 10.1109/ISCAS.2008.4541375
DO - 10.1109/ISCAS.2008.4541375
M3 - Conference contribution
AN - SCOPUS:51749085103
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 145
EP - 148
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -