Improving the power-delay performance in subthreshold source-coupled logic circuits

Armin Tajalli; Massimo Alioto; Elizabeth J. Brauer; Yusuf Leblebici

doi:10.1007/978-3-540-95948-9_3

Improving the power-delay performance in subthreshold source-coupled logic circuits

Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici

Informatics, Computing, and Cyber Systems, School of

Research output: Contribution to journal › Conference article › peer-review

Abstract

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

Original language	English (US)
Pages (from-to)	21-30
Number of pages	10
Journal	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	5349 LNCS
DOIs	https://doi.org/10.1007/978-3-540-95948-9_3
State	Published - 2009
Event	18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, Portugal Duration: Sep 10 2008 → Sep 12 2008

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

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10.1007/978-3-540-95948-9_3

Cite this

Improving the power-delay performance in subthreshold source-coupled logic circuits. / Tajalli, Armin; Alioto, Massimo; Brauer, Elizabeth J. et al.
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 5349 LNCS, 2009, p. 21-30.

Research output: Contribution to journal › Conference article › peer-review

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abstract = "Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.",

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AB - Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

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JO - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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Improving the power-delay performance in subthreshold source-coupled logic circuits

Abstract

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