High efficiency ring-LWE cryptoprocessor using shared arithmetic components

Tuy Nguyen Tan, Tram Thi Bao Nguyen, Hanho Lee

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total number of polynomial multipliers and polynomial adders used in the proposed ring-LWE cryptoprocessor are reduced. In addition, the processing time of NTT polynomial multiplier is speeded up by employing multiple-path delay feedback (MDF) architecture and deploying pipelined technique between all stages of NTT processes. As a result, the proposed architecture offers a great reduction in terms of the hardware complexity and computation latency compared with existing works. The implementation result for the proposed ring-LWE cryptoprocessor on Virtex-7 FPGA board using Xilinx VIVADO shows a significant decrease in the number of slices and LUTs compared with previous works. Moreover, the proposed ring-LWE cryptoprocessor offers higher throughput and efficiency than its predecessors.

Original languageEnglish (US)
Article number1075
Pages (from-to)1-12
Number of pages12
JournalElectronics (Switzerland)
Volume9
Issue number7
DOIs
StatePublished - Jul 2020
Externally publishedYes

Keywords

  • Cryptoprocessor
  • Multiple-path delay feedback
  • Pipelined
  • Ring-LWE
  • Shared arithmetic components

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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