Abstract
This paper presents a novel architecture to perform polynomial multiplication in ring learning with errors (ring-LWE) cryptosystems. By employing number theoretic transform (NTT) of the input polynomials simultaneously, the multiplication latency is significantly reduced. In addition, a multiple-path delay feedback (MDF) architecture is used to speed up the multiplication process. As a result, the proposed NTT multiplier offers a better value of area-latency product compared with that of previous studies. The simulation results for the security parameters n = 512 and q = 12,289 on Xilinx Virtex-7 FPGA show that the proposed multiplier uses only about 8.69% of the number of clock cycles required by previous works to completely perform the polynomial multiplication. Furthermore, the obtained area-latency product value of the proposed architecture is less than 45.3% of that of previous works.
Original language | English (US) |
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Pages (from-to) | 220-223 |
Number of pages | 4 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 20 |
Issue number | 2 |
DOIs | |
State | Published - Apr 2020 |
Externally published | Yes |
Keywords
- Cryptography
- Multiple-path delay feedback
- NTT polynomial multiplier
- Ring-LWE
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering