Abstract
Limitations on hardware resource consumption and throughput make the use of non-binary low-density parity-check (NB-LDPC) codes challenging in practical applications. This brief first proposes a novel check-node (CN) decoding algorithm called Hamming-distance trellis min-max (H-TMM) to reduce the complexity introduced by searching for two minimum values in previous TMM-based algorithms. Then, by taking advantage of the proposed algorithm and the number appearances of reliable values, a high-performance H-TMM-based NB-LDPC decoder architecture is presented. Experiments on the 32-ary (837, 726) NB-LDPC code confirmed that the proposed decoder can obtain a high throughput on less hardware resources compared with the state-of-the-art works while maintaining a competitive error-correcting performance. In particular, the proposed CN unit architecture reduced hardware resources by almost half compared to that in the latest decoder.
Original language | English (US) |
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Pages (from-to) | 2390-2394 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 70 |
Issue number | 7 |
DOIs | |
State | Published - Jul 1 2023 |
Externally published | Yes |
Keywords
- Hamming distance
- message compression
- non-binary low-density parity-check (NB-LDPC)
- Trellis min-max (TMM)
ASJC Scopus subject areas
- Electrical and Electronic Engineering