TY - JOUR
T1 - Generalised approach for predictive control with common-mode voltage mitigation in multilevel diode-clamped converters
AU - Yaramasu, Venkata
AU - Wu, Bin
AU - Rivera, Marco
AU - Narimani, Mehdi
AU - Kouro, Samir
AU - Rodriguez, Jose
N1 - Publisher Copyright:
© The Institution of Engineering and Technology 2015.
PY - 2015/8/1
Y1 - 2015/8/1
N2 - This study proposes a generalised approach based on model predictive strategy for the current control, dc-link capacitor voltages balancing, switching frequency reduction and common-mode voltage mitigation in multilevel diode-clamped converters. A generalised discrete-time model of the converters is presented, where all the control objectives are formulated in terms of the switching states. The control goals are expressed as a cost function, and with the help of suitable weighting factors these goals are met simultaneously. The cost function minimisation is used as criteria for choosing the best switching state which would be applied to the converter during next sampling interval. The real-time digital control issues such as computational burden and delay compensation are also discussed. The feasibility of the proposed method is verified by simulations in three- to six-level converters, and by experiments in three- and four-level converters.
AB - This study proposes a generalised approach based on model predictive strategy for the current control, dc-link capacitor voltages balancing, switching frequency reduction and common-mode voltage mitigation in multilevel diode-clamped converters. A generalised discrete-time model of the converters is presented, where all the control objectives are formulated in terms of the switching states. The control goals are expressed as a cost function, and with the help of suitable weighting factors these goals are met simultaneously. The cost function minimisation is used as criteria for choosing the best switching state which would be applied to the converter during next sampling interval. The real-time digital control issues such as computational burden and delay compensation are also discussed. The feasibility of the proposed method is verified by simulations in three- to six-level converters, and by experiments in three- and four-level converters.
UR - http://www.scopus.com/inward/record.url?scp=84938062214&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84938062214&partnerID=8YFLogxK
U2 - 10.1049/iet-pel.2014.0775
DO - 10.1049/iet-pel.2014.0775
M3 - Article
AN - SCOPUS:84938062214
SN - 1755-4535
VL - 8
SP - 1440
EP - 1450
JO - IET Power Electronics
JF - IET Power Electronics
IS - 8
ER -