Functional verification of ECL circuits including voltage regulators

Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.