Abstract
This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.
Original language | English (US) |
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Pages (from-to) | 118-125 |
Number of pages | 8 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 16 |
Issue number | 1 |
DOIs | |
State | Published - Feb 2016 |
Externally published | Yes |
Keywords
- Architecture
- Bit-serial
- Elliptic curve cryptography
- Point multiplication
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering