TY - GEN
T1 - Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption
AU - Duong-Ngoc, Phap
AU - Tan, Tuy Nguyen
AU - Lee, Hanho
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - This paper proposes a configurable architecture of butterfly unit (BU) supporting number theoretic transform (NTT) and inverse NTT (INTT) accelerators in the ring learning with error based homomorphic encryption. The proposed architecture is fully pipelined and carefully optimized the critical path delay. To compare with related works, several BU designs of different bit-size specific primes are synthesized and successfully placed-And-routed on the Xilinx Zynq UltraScale+ ZCU102 FPGA platform. Implementation results show that the proposed BU designs achieve 3× acceleration with more efficient resource utilization compared with previous works. Thus, the proposed BU architecture is worthwhile to develop NTTINTT accelerators in advanced homomorphic encryption systems.
AB - This paper proposes a configurable architecture of butterfly unit (BU) supporting number theoretic transform (NTT) and inverse NTT (INTT) accelerators in the ring learning with error based homomorphic encryption. The proposed architecture is fully pipelined and carefully optimized the critical path delay. To compare with related works, several BU designs of different bit-size specific primes are synthesized and successfully placed-And-routed on the Xilinx Zynq UltraScale+ ZCU102 FPGA platform. Implementation results show that the proposed BU designs achieve 3× acceleration with more efficient resource utilization compared with previous works. Thus, the proposed BU architecture is worthwhile to develop NTTINTT accelerators in advanced homomorphic encryption systems.
KW - butterfly unit
KW - homomorphic encryption
KW - Number theoretic transform (NTT)
KW - ring learning with error
UR - http://www.scopus.com/inward/record.url?scp=85123385684&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85123385684&partnerID=8YFLogxK
U2 - 10.1109/ISOCC53507.2021.9614034
DO - 10.1109/ISOCC53507.2021.9614034
M3 - Conference contribution
AN - SCOPUS:85123385684
T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021
SP - 345
EP - 346
BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International System-on-Chip Design Conference, ISOCC 2021
Y2 - 6 October 2021 through 9 October 2021
ER -