Abstract
We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1580-1583 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: Apr 30 1995 → May 3 1995 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering