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An Algorithm for Functional Verification of Digital ECL Circuits
Elizabeth J. Brauer
Informatics, Computing, and Cyber Systems, School of
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Keyphrases
Logic Circuit
100%
Functional Verification
100%
Emitter-coupled Logic
100%
Transistor
50%
Bipolar Transistor
50%
Steady State
25%
Downscaling
25%
Current Margin
25%
Transistor Model
25%
Voltage Margin
25%
Electrical Simulation
25%
Subcircuit
25%
Voltage Regulator
25%
Design Errors
25%
Current Sharing
25%
Spices
25%
Energy Consumption Reduction
25%
Circuit Description
25%
Computationally Efficient Algorithms
25%
Transistor Level
25%
Switching Characteristics
25%
Steady-state Voltage
25%
CPU Time
25%
Verification Algorithm
25%
Node Voltage
25%
Current-voltage
25%
Computer-aided Design Tools
25%
Engineering
Emitter Coupled Logic Circuits
100%
Bipolar Transistor
50%
Electric Power Utilization
25%
Subcircuit
25%
Voltage Regulator
25%
Computer Aided Design
25%
Design Tool
25%
Broader Class
25%
SPICE
25%
State Device
25%
Node Voltage
25%