TY - JOUR
T1 - A scalable LDPC decoder ASIC architecture with bit-serial message exchange
AU - Brandon, Tyler
AU - Hang, Robert
AU - Block, Gary
AU - Gaudet, Vincent C.
AU - Cockburn, Bruce
AU - Howard, Sheryl
AU - Giasson, Christian
AU - Boyle, Keith
AU - Goud, Paul
AU - Zeinoddin, Siavash Sheikh
AU - Rapley, Anthony
AU - Bates, Stephen
AU - Elliott, Duncan
AU - Schlegel, Christian
N1 - Funding Information:
Anthony Rapley received the B.A.Sc. degree in Electronic Systems Engineering in 2002 from the University of Regina and the M.Sc. in Electrical and Computer Engineering in 2006 from the University of Alberta. His graduate studies were funded by the Natural Sciences and Engineering Research Council of Canada (NSERC), the Alberta Informatics Circle of Research Excellence (iCORE), and the University of Alberta. From 2004 to 2007, he worked as a functional verifier of system-on-a-chip ASICs at PMC-Sierra in Saskatoon, Saskatchewan, and he is currently employed as an embedded system developer with Case/ New Holland in Saskatoon. His current interests include error control coding, SoC design and verification and controller area networks.
Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2008/5
Y1 - 2008/5
N2 - We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250 Mbps, a core area of 6.96 mm2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56 nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.
AB - We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250 Mbps, a core area of 6.96 mm2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56 nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.
KW - Bit-serial arithmetic
KW - Error-control codes
KW - Iterative decoding
KW - Low-density parity check codes
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U2 - 10.1016/j.vlsi.2007.07.003
DO - 10.1016/j.vlsi.2007.07.003
M3 - Article
AN - SCOPUS:43049181464
SN - 0167-9260
VL - 41
SP - 385
EP - 398
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
IS - 3
ER -