A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Tyler Brandon, Robert Hang, Gary Block, Vincent C. Gaudet, Bruce Cockburn, Sheryl Howard, Christian Giasson, Keith Boyle, Paul Goud, Siavash Sheikh Zeinoddin, Anthony Rapley, Stephen Bates, Duncan Elliott, Christian Schlegel

Research output: Contribution to journalArticlepeer-review

29 Scopus citations


We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250 Mbps, a core area of 6.96 mm2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56 nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.

Original languageEnglish (US)
Pages (from-to)385-398
Number of pages14
JournalIntegration, the VLSI Journal
Issue number3
StatePublished - May 2008


  • Bit-serial arithmetic
  • Error-control codes
  • Iterative decoding
  • Low-density parity check codes

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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