TY - JOUR
T1 - A hybrid CPU/GPU approach for optimizing sorting throughput
AU - Gowanlock, Michael
AU - Karsin, Ben
N1 - Funding Information:
We thank the University of Hawai‘i for the use of their cluster, UHHPC. This material is based upon work supported by the National Science Foundation under grants 1533823 and 1745331 and Fonds de la Recherche Scientifique-FNRS under grant no. MISU F 6001 1 .
Funding Information:
We thank the University of Hawai‘i for the use of their cluster, UHHPC. This material is based upon work supported by the National Science Foundation under grants 1533823 and 1745331 and Fonds de la Recherche Scientifique-FNRS under grant no. MISU F 6001 1.
Publisher Copyright:
© 2019 Elsevier B.V.
PY - 2019/7
Y1 - 2019/7
N2 - The GPU is an effective architecture for sorting due to its massive parallelism and high memory bandwidth. However, for input datasets that exceed global memory capacity, the communication overhead between host (CPU) and GPU may degrade the overall performance of heterogeneous approaches. Thus, to achieve performance gains over multi-core parallel CPU algorithms, heterogeneous sorting using the GPU needs to obviate communication overheads. We provide a detailed overview of current host-GPU data transfer mechanisms and advance several methods of mitigating the associated performance bottlenecks. Using these methods, we develop a heterogeneous CPU/GPU sorting algorithm that effectively exploits the architecture. Furthermore, we demonstrate that, while out-of-place GPU sorting achieves the best performance, an in-place sort has the potential to further reduce some host-side bottlenecks, which encourages several future research priorities. Our approaches mitigate several bottlenecks, as demonstrated on single- and dual-GPU platforms, achieving speedups up to 3.47× over the parallel reference implementation on the CPU. We discuss future research for heterogeneous sorting in the multi-GPU NVLink era.
AB - The GPU is an effective architecture for sorting due to its massive parallelism and high memory bandwidth. However, for input datasets that exceed global memory capacity, the communication overhead between host (CPU) and GPU may degrade the overall performance of heterogeneous approaches. Thus, to achieve performance gains over multi-core parallel CPU algorithms, heterogeneous sorting using the GPU needs to obviate communication overheads. We provide a detailed overview of current host-GPU data transfer mechanisms and advance several methods of mitigating the associated performance bottlenecks. Using these methods, we develop a heterogeneous CPU/GPU sorting algorithm that effectively exploits the architecture. Furthermore, we demonstrate that, while out-of-place GPU sorting achieves the best performance, an in-place sort has the potential to further reduce some host-side bottlenecks, which encourages several future research priorities. Our approaches mitigate several bottlenecks, as demonstrated on single- and dual-GPU platforms, achieving speedups up to 3.47× over the parallel reference implementation on the CPU. We discuss future research for heterogeneous sorting in the multi-GPU NVLink era.
KW - GPGPU
KW - Heterogeneous architectures
KW - Sorting
UR - http://www.scopus.com/inward/record.url?scp=85064271034&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85064271034&partnerID=8YFLogxK
U2 - 10.1016/j.parco.2019.01.004
DO - 10.1016/j.parco.2019.01.004
M3 - Article
AN - SCOPUS:85064271034
SN - 0167-8191
VL - 85
SP - 45
EP - 55
JO - Parallel Computing
JF - Parallel Computing
ER -